In present designs of semiconductor integrated circuits and particularly calculator integrated circuits, an input/output (I/O) reconfiguration of the underlying chip design typically necessitates a major redesign, or at least a relayout of the bar. Ideally, it is desirable to be able to redefine and redesign the I/O quickly and easily without major redesign, and without major relayout. Existing integrated circuit designs locate the desired buffer physically close to the pin to which it is to be coupled, and special select and control logic, which may or may not be physically located adjacent to the I/O buffer, is built to control and select the buffer. The control logic is comprised of power, data, and select/control lines which are coupled to the controlled buffer. If it is then desired to assign new pin locations to the buffer functions, it is necessary to physically move the existing buffers to the desired bonding pad locations, or to add new buffers, in either case requiring a relayout of the select/control lines of the control logic. This is a major design task which consumes much time and man power, and inhibits optimizing of integrated circuit designs by optimizing pin-outs of the integrated circuits for compatibility with the specific design in which the circuits will be used.